Pipelined Fixed-Point Function Evaluation Unit

RTL → Layout · 500 MHz · 2026

y = ((a−b)·d·log₂₀₄₈(1+c)) / (a+b+1)

11-bit unsigned a, b, c; 10-bit unsigned d; 11-bit signed two’s-complement y.
Ports only: a[10:0], b[10:0], c[10:0], d[9:0], clk → y[10:0]

|error| < ±1 at 500 MHz (100 ps jitter). Full RTL-to-layout flow: verification, synthesis, STA, P&R, SDF simulation. Zero Calibre DRC violations; LVS clean; EDP (latency × power) optimized.

• Verilog HDL
• Design Compiler
• Innovus
• Calibre
• STA

Circuit Model Exploration Device Based on MSPM0G3507

Third Prize (Guangdong Division), 2025 National Undergraduate Electronic Design Contest

Designed, implemented, and debugged the overall software: DDS signal control and AGC amplitude adjustment, automatic frequency sweep with ADC acquisition and filtering, and circuit type recognition based on -3 dB cutoff frequency.

• MSPM0G3507
• C
• DDS
• ADC
• Embedded